The use of barrier coatings on microelectronic integrated circuits (ICs) and in printed wiring assemblies is challenged by the finer feature size that is the result of advancing circuit design technology. In general, barrier coatings are expected to offer some functionality for security, thermal management, physical protection, electrical isolation, electromagnetic impulse protection, and environmental isolation. However, high density circuitry in ICs and circuit card assemblies (CCAs) include fine metallization lines and stacked, fine-pitch interconnect. These fine metallization lines and stacked fine-pitch interconnects make it difficult to enabling coating applications and for meeting performance requirements of the coated hardware. Finer circuit features are more vulnerable to the mechanical stresses imposed by the coating during the applied coating cure, qualification testing, and throughout the operational life of the coated hardware. Moreover, full encapsulation of the finer circuit interconnect features are hampered by flow restrictions of the applied coating and filler through the fine pitch of wirebonds and similar interconnect features. The electronics systems industry, in particular, needs synergistic security enhancements built into the material advancements that can be used to solve the problems of coating applications in high density, fine-featured, circuit architecture.
For the reasons stated above and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an effective and efficient method of coating high density fine featured circuit architecture that provides security.